1. Field of the Invention
This invention is related to the field of integrated circuits, and more particularly, to testing storage structures of integrated circuits.
2. Description of the Related Art
The adherence of the development of integrated circuit technology to Moore's Law over the past few decades has led to the capacity to fabricate highly complex integrated circuits (IC) including tens of millions of transistors on a single die. With wafer size increasing to 300 mm and beyond, the number of ICs that can be manufactured on a single wafer may range from hundreds to thousands. Therefore each processed wafer represents a substantial value in terms of potentially saleable finished product.
ICs on processed wafers are typically tested for both functionality and performance. During functional testing, if a particular IC is determined at this stage to be non-functional, then when the wafer is sawn into individual die, the die including that IC may be discarded thus avoiding the cost associated with attaching it to a lead frame, wire bonding, and packaging. Performance testing at the wafer stage may indicate that ICs formed on different parts of the wafer have different maximum operating speeds. Performance differences may be due to variations in process, mask alignment inaccuracies, and other manufacturing variables. The die may be sorted by operating speed and packaged/sold accordingly.
Another reason for wafer stage testing of ICs is to determine yield for feedback used in controlling the manufacturing process. The chemical and mechanical processes used in the manufacture of an IC wafer are numerous and may be prone to deviation from nominal. Typically, several layers are deposited on/in the surface of the wafer by thermal growth, chemical vapor deposition, photolithography, ion implantation and other methods. The results of thermal growth and chemical vapor deposition processes may be adversely affected by variations in the wafer's environment during processing. Fluctuations in oven temperature or the chemical composition of the atmosphere to which the wafer is exposed may produce ICs that are non-functional or that do not operate at frequencies as high as specified.
Processes that involve masking portions of the wafer such as photolithography, ion implantation, etc. may be susceptible to problems caused by mask misalignment, improper beam angle, variations in smoothness/flatness of the wafer surface etc. Variations in the parameters of these types of processes may result in ICs manufactured on one portion of the wafer having different operational characteristics from those manufactured on a different portion of the wafer. For example, a slight rotational mask misalignment may result in fully functional ICs being produced in and around the center of the wafer, while non-functional or severely degraded circuits are formed near the wafer's edge.
Since changes in process parameters may occur at any time during the manufacturing process it may be important to perform wafer stage testing periodically to discover the effects of such changes in a timely fashion. A wafer probe may be used to contact multiple probe points manufactured on the wafer expressly for this purpose. Automated test equipment (ATE) may provide signals to and receive signals from ICs on the wafer through one or more probes. In a typical test environment using the wafer probe, the ATE may provide stimulus in the form of clock signals and data to the ICs on the wafer. In addition, the ATE may receive results from the ICs. Since the signals produced by the ATE must typically travel several feet from the point at which they are generated to the point at which they enter the wafer, there may be a physical limit on the frequency of the signals that can be supplied to the ICs using this methodology. For example, high speed ICs may be designed to operate at clock frequencies of tens of Gigahertz or more. Many types of ATE may not be capable of supplying signals of these frequencies to a wafer. Therefore, usual practice may be to perform wafer stage testing at frequencies, which the ATE is capable of supplying and which may be significantly lower than the specified operating frequency of the ICs. This type of testing may be inadequate to discover problems at the various process corners.